The SFI-S IP Reference Design targets Xilinx 7 series FPGAS Using GTX or GTH serial transceivers to implement a bidirectional 10 data channel SFI-S interface at 111.8 Gb/s.
Wednesday, September 26, 2012
Xilinx SFI-S IP Reference Design
Xilinx SFI-S IP Reference Design Video Clips. Duration : 3.08 Mins.
The SFI-S IP Reference Design targets Xilinx 7 series FPGAS Using GTX or GTH serial transceivers to implement a bidirectional 10 data channel SFI-S interface at 111.8 Gb/s.
The SFI-S IP Reference Design targets Xilinx 7 series FPGAS Using GTX or GTH serial transceivers to implement a bidirectional 10 data channel SFI-S interface at 111.8 Gb/s.
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